1. Field of the Invention
The present invention relates to the field of integrated circuit memory storage devices, and more particularly, it relates to a memory cell arrangement and production of memory cell arrangements.
2. Description of the Related Art
In view of the rapid development in computer technology, there is a demand for ever faster, denser and better programmable, erasable and readable memory cells.
A nonvolatile so-called channel hot electron (CHE) memory cell has a field effect transistor with an electrically conductive floating gate layer between a gate insulating layer and a control gate. Electrical charge carriers are introduced into the CHE memory cell by the injection of hot channel electrons. The information that is stored in the CHE memory cell is coded according to the presence or the absence of charge carriers in the floating gate layer. One or more “hot”, or sufficiently greatly accelerated, electrons or holes in the vicinity of a drain region can pass through the gate insulating layer into the floating gate layer. On account of an electrically insulating region surrounding the floating gate, the introduced electrical charge carriers are protected against flowing away from the floating gate layer and thus remain permanently in the floating gate layer.
FIG. 1 illustrates a known floating gate memory cell 100. The floating gate memory cell 100 is integrated in a p-doped silicon substrate 101. An n-doped well 102 is formed in the p-doped silicon substrate 101. A p-doped well 103 is formed in the n-doped well 102. A first source/drain region 104 is formed as an n+-doped region in a first surface region of the p-doped well 103. Furthermore, a second source/drain region 105 is formed as an n+-doped region in a second surface region of the p-doped well 103. A channel region 106 is formed in the surface region of the p-doped well 103 between the source/drain regions 104, 105. By means of an electrically insulating region 107, a floating gate region 108 arranged above the channel region 106 is electrically insulated from the channel region 106, and a control gate 109 arranged above the floating gate region 108 is electrically insulated from the floating gate region 108. By means of Shallow Trench Isolation (“STI”) regions 110 arranged laterally with respect to the floating gate memory cell 101, the floating gate memory cell 100 is electrically decoupled from adjacent memory cells (not shown in FIG. 1) of a memory cell arrangement. By means of contact-connection elements 111, a predeterminable electrical potential can in each case be applied to the source/drain regions 104, 105 and to the control gate 109. A pn junction 112 is formed between the n-doped well 102 and the p-doped well 103.
In order to introduce electrical charge carriers into the floating gate 108 of the nonvolatile floating gate memory cell 100, hot electrons are injected from the substrate using a pn junction 112 that is electrically biased in the forward direction. For this purpose, the control gate 109 is brought to a positive electrical potential having a sufficiently large magnitude. On account of the (capacitive) coupling of the floating gate 108 and the control gate 109, said electrical potential also acts on the floating gate 108. The pn junction 112 between the n-doped well 102 and the p-doped well 103 is electrically biased in such a way that electrons are injected from the n-doped well 102 into the p-doped well 103. On account of the positive potential at the floating gate 108, electrons are accelerated to the channel region 106 and can be injected into the floating gate 108 through the gate insulating layer formed by means of the electrically insulating region 107.
An item of information can be programmed into the memory cell 100. The floating gate memory cell 100 of FIG. 1 has the disadvantage that the entire pn junction 112 has to be biased across a large lateral width. This leads to high energy consumption during programming, erasing and reading of the memory cell 100, which is disadvantageous in particular for low-power applications.
FIG. 2 illustrates a test arrangement 200 that is known for examinations of the reliability of components. In particular, the test arrangement 200 serves for checking the quality or reliability of a gate insulating layer in a field effect transistor formed beforehand. The test arrangement 200 is integrated on and in a p-doped silicon substrate 201, where a field effect transistor 202 is integrated in the test arrangement 200. The field effect transistor contains a first source/drain region 203 formed in a first surface region of the p-doped silicon substrate 201 and a second source/drain region 204 formed in a second surface region of the p-doped silicon substrate 201. Both source/drain regions 203, 204 are n+-doped regions. A channel region 208 is formed between the two source/drain regions 203, 204. A gate region 206 is formed above the channel region 208 and is electrically isolated from the channel region 208 by means of a gate insulating layer, which is part of an electrically insulating region 205. Provision is made of contact-connection elements 207 for applying defined electrical potentials to the source/drain regions 203, 204 and to the gate region 206. Laterally with respect to the field effect transistor 202, an additional n+-doped region 209 is provided in another surface region of the silicon substrate 201 and can be driven electrically by means of another contact-connection element 210. As indicated schematically in FIG. 2, electrical charge carriers, namely electrons, can be injected from the n+-doped region 209 via the p-doped silicon substrate 201 and the channel region 208 through the gate insulating layer possibly right into the gate region 206 by means of the application of 0V or a positive electrical potential to the source/drain regions 203, 204 and a stronger positive electrical potential in comparison with said positive potential to the gate region 206 and also a negative electrical potential to the n+-doped region 209.
The test arrangement of FIG. 2 is only suitable for testing the functionality of a field effect transistor 202 formed using semiconductor-technological processing, in particular for testing the functionality of the gate insulating layer of the field effect transistor. The test arrangement 200 leads to very large area consumption on a silicon substrate 201.